1 ps8543 06/11/01 v ddq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 35 36 34 33 32 31 30 29 28 27 26 25 fbout gnd gnd gnd fbin fbin pwrdwn gnd gnd y9 y8 y8 fbout y7 y7 y6 y6 y5 y5 y9 gnd gnd gnd y0 y0 y1 y1 v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq gnd clk clk y2 y2 gnd y3 y3 y4 y4 agnd av dd product description PI6CV857l pll clock device is developed for registered ddr dimm applications this pll clock buffer is designed for 2.5 v ddq and 2.5v av dd operation and differential data input and output levels. package options include plastic thin shrink small-outline package (tssop).the device is a zero delay buffer that distributes a differ- ential clock input pair (clk, clk) to ten differential pairs of clock outputs (y[0:9], y[0:9]) and one differential pair feedback clock outputs (fbout,fbout) . the clock outputs are controlled by the input clocks (clk, clk), the feedback clocks (fbin,fbin), the 2.5v lvcmos input (pwrdwn) and the analog power input (av dd ). when input pwrdwn is low while power is applied, the input receivers are disabled, the pll is turned off and the differential clock outputs are 3-stated. when the av dd is strapped low, the pll is turned off and bypassed for test purposes. when the input frequency falls below a suggested detection fre- quency that is below the operating frequency of the pll, the device will enter a low power mode. an input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the pwrdwn input is low. the pll in the PI6CV857l clock driver uses the input clocks (clk, clk) and the feedback clocks (fbin,fbin) to provide high-perfor- mance, low-skew, low-jitter output differential clocks (y[0:9], y[0:9]). the PI6CV857l is also able to track spread spectrum clocking for reduced emi. product features ? pll clock distribution optimized for double data rate sdram applications. ? distributes one differential clock input pair to ten differential clock output pairs. ? inputs (clk,clk) and (fbin,fbin): sstl_2 ? input pwrdwn: lvcmos ? outputs (yx, yx), (fbout, fbout): sstl_2 ? external feedback pins (fbin,fbin) are used to synchronize the outputs to the clock input. ? operates at av dd = 2.5v for core circuit and internal pll, and v ddq = 2.5v for differential output drivers ? available packages: plastic 48-pin tssop block diagram/pin configuration PI6CV857l pll clock driver for 2.5v ddr-sdram memory 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 y0 y0 y1 pwrdwn av dd fbin fbin clk clk pll y1 y2 y2 y3 y3 y4 y4 y5 y5 y6 y6 y7 y7 y8 y8 y9 y9 fbout fbout powerdown and test logic 48-pin a
2 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory function table s t u p n is t u p t u oe t a t s l l p v a d d gk l ck l cyy t u o b ft u o b f d n ghlhlhlh f f o / d e s s a p y b d n ghhlhlhl f f o / d e s s a p y b xllhzzzz f f o xlhlzzzz f f o ) m o n ( v 5 . 2hlhlhlhn o ) m o n ( v 5 . 2hhlhlhln o ) m o n ( v 5 . 2x z h m 0 2 < ) 1 ( zzz z f f o notes: for testing and power saving purposes, PI6CV857l will power down if the frequency of the reference inputs clk, clk is well below the operating frequency range. the maximum power down clock frequency is below 20 mhz. for example, PI6CV857l will be powered down when the clk,clk stop running. z = high impedance x = don?t care e m a n n i p. o n n i pe p y t o / in o i t p i r c s e d k l c k l c 3 1 4 1 it u p n i k c o l c e c n e r e f e r x y6 4 , 4 4 , 9 3 , 9 2 , 7 2 , 2 2 , 0 2 , 0 1 , 5 , 3 o . s t u p t u o k c o l c x y7 4 , 3 4 , 0 4 , 0 3 , 6 2 , 3 2 , 9 1 , 9 , 6 , 2. s t u p t u o k c o l c t n e m e l p m o c t u o b f t u o b f 2 3 3 3 t u p t u o k c a b d e e f t n e m e l p m o c d n a , t u p t u o k c a b d e e f n i b f n i b f 6 3 5 3 i t u p t u o k c a b d e e f t n e m e l p m o c d n a , t u p t u o k c a b d e e f n w d r w p7 3 , 0 = n w d r w p n e h w . s t u p t u o x y d n a x y l l a r o f e l b a s i d t u p t u o d n a n w o d r e w o p a o t d e l b a s i d e r a s t u p t u o k c o l c l a i t n e r e f f i d e h t d n a n w o d d e r e w o p s i t r a p e h t n u r d n a d e l b a n e e r a s t u p t u o k c o l c l a i t n e r e f f i d l l a , 1 = n w d r w p n e h w . e t a t s - 3 . k l c s a y c n e u q e r f e m a s e h t t a v q d d 5 4 , 8 3 , 4 3 , 8 2 , 1 2 , 5 1 , 2 1 , 1 1 , 4 r e w o p . o / i r o f y l p p u s r e w o p v a d d 6 1 v a . y l p p u s r e w o p e r o c / g o l a n a d d g n i t s e t r o f l l p e h t s s a p y b o t d e s u e b n a c v a n e h w . s e s o p r u p d d s i k l c d n a d e s s a p y b s i l l p , d n u o r g o t d e p p a r t s s i . s t u p t u o e c i v e d e h t o t y l t c e r i d d e r e f f u b d n g a7 1 d n u o r g y r t i u c r i c e r o c / g o l a n a e h t r o f e c n e r e f e r d n u o r g e h t s e d i v o r p . d n u o r g e r o c / g o l a n a d n g8 4 , 2 4 , 1 4 , 1 3 , 5 2 , 4 2 , 8 1 , 8 , 7 , 1d n u o r g pinout table
3 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory absolute maximum ratings (over operating free-air temperature range) note : stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. l o b m y sr e t e m a r a p. n i m. x a ms t i n u v q d d v a , d d e g n a r e g a t l o v y l p p u s e r o c / g o l a n a d n a e g n a r e g a t l o v y l p p u s o / i5 . 0 ?6 . 3 v v i e g n a r e g a t l o v t u p n i5 . 0 ? v q d d 5 . 0 v o e g n a r e g a t l o v t u p t u o5 . 0 ? g t s te r u t a r e p m e t e g a r o t s5 6 ?0 5 1 o c notes: 1. the pll is able to handle spread spectrum induced skew. 2. operating clock frequency indicates a range over which the pll is able to lock, but in which the clock is not required to mee t the other timing parameters. (used for low-speed debug). 3. application clock frequency indicates a range over which the pll meets all of the timing parameters. timing requirements (over recommended operating free-air temperature) l o b m y sn o i t p i r c s e d v a d d v , q d d v 2 . 0 v 5 . 2 = s t i n u . n i m. x a m f k c y c n e u q e r f k c o l c g n i t a r e p o ) 2 , 1 ( 0 60 7 1 z h m y c n e u q e r f k c o l c n o i t a c i l p p a ) 3 ( 5 90 7 1 t c d e l c y c y t u d k c o l c t u p n i0 40 6% t b a t s p u r e w o p r e t f a e m i t n o i t a z i l i b a t s l l p 0 0 1s
4 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory r e t e m a r a ps n o i t i d n o c t s e ta d d v v , q d d . n i m. p y t. x a ms t i n u v k i s t u p n i l l ai i a m 8 1 ? =v 3 . 22 . 1 ?v i i n i b f , k cv i v = q d d d n g r o v 7 . 2 0 1 a n w d r w pv i v = q d d d n g r o i q d d v f o t n e r r u c y l p p u s c i m a n y d q d d v d d v 7 . 2 =0 0 3a m t n e r r u c y l p p u s c i t a t s r o z h m 0 2 < k c & k c w o l = n w d r w p ) 1 ( 0 0 1a i d d a v a f o t n e r r u c y l p p u s c i m a n y d d d v d d v 7 . 2 =2 1a m t n e r r u c y l p p u s c i t a t s r o z h m 0 2 < k c & k c w o l = n w d r w p ) 1 ( 0 0 1a c i k c d n a k c v i v = d d d n g r ov 5 . 20 . 20 . 3f p n i b f d n a n i b f l o b m y sr e t e m a r a p. n i m. m o n. x a ms t i n u v a d d e g a t l o v y l p p u s e r o c / g o l a n a3 . 25 . 27 . 2 v v q d d e g a t l o v y l p p u s t u p t u o3 . 25 . 27 . 2 v l i n i p n w d r w p r o f e g a t l o v t u p n i l e v e l - w o l 3 . 0 ?7 . 0 v h i n i p n w d r w p r o f e g a t l o v t u p n i l e v e l - h g i h7 . 1v q d d 3 . 0 + v h o e g a t l o v t u p t u o l e v e l - h g i h8 . 1v q d d v l o e g a t l o v t u p t u o l e v e l - w o l05 . 0 v x i e g a t l o v g n i s s o r c r i a p - l a i t n e r e f f i d t u p n iv ( q d d 2 . 0 ? ) 2 /v ( q d d 2 . 0 + ) 2 / v x o t u p n i k c o l c m a r d e h t t a e g a t l o v g n i s s o r c r i a p - l a i t n e r e f f i d t u p t u ov ( q d d 2 . 0 ? ) 2 /v ( q d d 2 . 0 + ) 2 / v n i l e v e l e g a t l o v t u p n i 3 . 0 ?v q d d 3 . 0 + v d i k c d n a k c n e e w t e b e g a t l o v l a i t n e r e f f i d t u p n i 6 3 . 0v q d d 6 . 0 + v d o t u o b f & t u o b f d n a ] n [ y & ] n [ y n e e w t e b e g a t l o v l a i t n e r e f f i d t u p t u o7 . 0v q d d 6 . 0 + t a e r u t a r e p m e t r i a e e r f g n i t a r e p o00 7c dc specifications recommended operating conditions electrical characteristics note : 1. the maximum power-down clock frequency is below 20 mhz.
5 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory ac specifications switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( see figure 1 & 2 ) r e t e m a r a pn o i t p i r c s e dm a r g a i d v a c c v , q d d v 2 . 0 v 5 . 2 = s t i n u . n i m. m o nx a m ) c c ( t i j tr e t t i j e l c y c - o t - e l c y c3 e r u g i f e e s5 7 ?5 7 s p ( t q )t e s f f o e s a h p c i t a t s ) 1 ( 4 e r u g i f e e s0 5 ?00 5 ) o ( k s tw e k s k c o l c t u p t u o5 e r u g i f e e s0 0 1 ) r e p ( t i j tr e t t i j d o i r e p6 e r u g i f e e s5 7 ?5 7 ) r e p h ( t i j tr e t t i j d o i r e p - f l a h7 e r u g i f e e s0 0 1 ?0 0 1 ) i ( l s te t a r w e l s k c o l c t u p n i ) 2 ( 8 e r u g i f e e s0 . 10 . 2 s n / v ) o ( l s te t a r w e l s k c o l c t u p t u o ) 2 ( 8 e r u g i f e e s0 . 10 . 2 g n i w o l l o f e h t h t i w s r e z i s e h t n y s c s s g n i t r o p p u s e l i h w s r e t e m a r a p e v o b a e h t l l a g n i t e e m f o e l b a p a c s i l 7 5 8 v c 6 i p e h t n o l l p e h t s r e t e m a r a p ) 3 ( . y c n e u q e r f n o i t a l u d o m c s s0 0 . 0 30 0 . 0 5z h k n o i t a i v e d y c n e u q e r f t u p n i k c o l c c s s0 0 . 00 5 . 0 ?% h t d i w d n a b p o o l l l p2z h m e l g n a e s a h p 1 3 0 . 0 ?s e e r g e d notes: 1. static phase offset does not include jitter. 2. the slew rate is determined from the ibis model with test load shown in figure1. 3. the ssc requirements meet the intel pc100 sdram registered dimm specification.
6 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory figure 2. output load test circuit figure 1. ibis model output load Cv ddq /2 v ddq /2 Cv ddq /2 Cv ddq /2 c = 14pf r = 10 w r = 10 w z= 60 w z= 60 w z= 50 w z= 50 w c = 14pf gnd gnd r = 50 w r = 50 w scope PI6CV857 v dd PI6CV857 z=60 w z=60 w r=120 w ddr sdram ddr sdram
7 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory figure 3. cycle-to-cycle jitter figure 4. static phase offset figure 5. output skew fbin fbin ck ck t ( ) n t ( ) n+1 t = ? 1 n=n t ( ) n n (n is a large number of samples) t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 t cycle n yx,fbout yx,fbout t sk(o) yx yx yx, fbout yx, fbout
8 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory figure 6. period jitter figure 7. half-period jitter figure 8. input and output slew rates clock inputs and outputs v id t sl(i), t sl(o) 80% 20% t sl(i), t sl(o) 80% 20% yx, fbout yx, fbout yx, fbout yx, fbout t cycle n f o 1 t jit(per) = t cycle n f o 1 yx, fbout yx, fbout t half period n t n+1 half period f o 1 t jit(hper) = t half period n 2*f o 1
9 ps8543 06/11/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6CV857l pll clock driver for 2.5v ddr-sdram memory pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com packaging mechanical: 48-pin tssop .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc e d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a p a l 7 5 8 v c 6 i p8 4 ap o s s t e d i w l i m - 0 4 2 , n i p - 8 4 ordering information
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